1. Field of the Invention
The present invention relates to a technique for inspecting a defect of a pattern formed on a substrate.
2. Description of the Background Art
Conventionally, in order to detect a defect of a circuit pattern formed on a substrate such as a semiconductor wafer, an appearance inspection in which an image of the circuit pattern is acquired and a defective portion is extracted on the basis of a comparison with a reference image serving as a reference has been performed. Recently, for high-speed inspection, an appearance inspection apparatus allowing parallel data processing, which comprises a plurality of processor elements, has been proposed (for example, in Japanese Patent Application Laid Open Gazette No. 2011-028410).
Specifically, in the appearance inspection apparatus disclosed in Japanese Patent Application Laid Open Gazette No. 2011-028410, when an image which is scanned by a line sensor is divided, a general control computer sets conditions for allocating the divided images to the plurality of processor elements. Then, an image allocation part divides the image and transfers the divided images to the processor elements, respectively, in accordance with the allocation conditions. Each of the processor elements performs a prescribed inspection and extracts a defect of the circuit pattern.
Further, the appearance inspection apparatus disclosed in Japanese Patent Application Laid Open Gazette No. 2011-028410 controls a range of an image to be cut out on the basis of the processing capability of the processor elements and the computational load of each inspection algorithm. The appearance inspection apparatus thereby imposes uniform load onto the processor elements to efficiently use the processing capabilities of the processor elements.
In recent years, inspection of substrates on which very small dies (chips) such as power devices, organic ELs, LEDs or the like are formed has been increasingly demanded. When a substrate on which such a very small die is formed is inspected in the appearance inspection apparatus disclosed in Japanese Patent Application Laid Open Gazette No. 2011-028410, the size of the divided image disadvantageously becomes very small in some cases. In such cases, in the background-art appearance inspection apparatus, since an enormous number of image transfers occur, the time of overhead for communication occurring in the transfer of the image data, or the like, is disadvantageously made longer relatively to the time for transfer of the image data. Therefore, there is a possibility of significantly decreasing the transfer efficiency due to the overhead. When the transfer efficiency decreases, the inspection time is consequently prolonged, and therefore it becomes hard to perform an efficient inspection.
Further, in the appearance inspection apparatus disclosed in Japanese Patent Application Laid Open Gazette No. 2011-028410, in order to impose the computational load onto the processor elements in a good balance, it is necessary to perform an experimental inspection in advance to control the load ratio for the processor elements. Furthermore, if the processor elements are increased in order to reduce the inspection time, this further requires a complicated operation for controlling the load ratio for the processor elements again.
In the appearance inspection apparatus disclosed in Japanese Patent Application Laid Open Gazette No. 2011-028410, prior to the inspection, an image which is cut out and a processor element for processing the image are associated with each other. Therefore, the processing time sometimes varies depending on the size or the amount of defects included in the image which is cut out, and there is a strong possibility of breaking the balance of the loads imposed on the plurality of processor elements.